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NS2 IEEE Projects 2019-2020 Chennai
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2019 – 2020
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About IEEE NS2 Projects
Welcome to the 1 Crore Project Centre Chennai, your premier destination for groundbreaking 2019-2020 IEEE NS2 projects. As technology continues to advance at an unprecedented pace, our dedicated team is committed to helping you stay at the forefront of innovation. We specialize in offering a diverse range of projects tailored to the intricate requirements of the NS2 framework. With our extensive experience and cutting-edge resources, we provide a unique platform for students and researchers to explore, develop, and excel in the dynamic field of network simulation.
At 1 Crore Project Centre Chennai, we understand the importance of staying updated with the latest trends and developments in the world of networking. Our keyword, 2019-2020 IEEE NS2 projects encapsulates the essence of our offerings. We empower you to delve into projects that not only align with industry standards but also push the boundaries of what is possible. With our guidance and support, you can embark on a journey of innovation and discovery, making a significant impact in the field of network simulation.
Our commitment to excellence extends beyond project development. We foster an environment of collaboration, providing you with the tools and knowledge to succeed. When you choose us as your project partner, you gain access to a wealth of resources, expert mentors, and a dedicated support network. Join us at the 1 Crore Project Centre Chennai and unlock the potential of 2019-2020 IEEE NS2 projects. Let’s together shape the future of networking through innovation and knowledge.
Low power
15 project titles
- Energy efficient reduce and rank using input adaptive approximations
- Enfire: a spatio-temporal fine-grained reconfigurable hardware
- Sign-magnitude encoding for efficient vlsi realization of decimal multiplication
- Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication
- Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers
- A way-filtering-based dynamic logical-associative cache architecture for low-energy consumption
- Resource-efficient sram-based ternary content addressable memory
- A high-efficiency 6.78-mhz full active rectifier with adaptive time delay control for wireless power transmission
High speed data transmission
15 project titles
- High-speed and low-latency ecc processor implementation over gf(2m) on fpga
- A 2.5-ps bin size and 6.7-ps resolution fpga time-to-digital converter based on delay wrapping and averaging
- Comedi: combinatorial election of diagnostic vectors from detection test sets for logic circuits
- Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding
- A 2.4-3.6-ghz wideband sub-harmonically injection-locked pll with adaptive injection timing alignment technique
- fast automatic frequency calibrator using an adaptive frequency search algorithm
- A 65-nm cmos constant current source with reduced pvt variation
- High-speed parallel lfsr architectures based on improved state-space transformations
- Scalable approach for power droop reduction during scan-based logic bist
- Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations
- Stochastic implementation and analysis of dynamical systems similar to the logistic map
Area efficient/ timing & delay reduction
15 project titles
- Roba multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing
- Vlsi design of 64bit * 64bit high performance multiplier with redundant binary encoding
- A method to design single error correction codes with fast decoding for a subset of critical bits
- Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs
- Efficient soft cancelation decoder architectures for polar codes
- Low-complexity digit-serial multiplier over gf(2m) based on efficient toeplitz block toeplitz matrix-vector product decomposition
- Efficient designs of multiported memory on fpga
- Hybrid lut multiplexer fpga logic architectures
- Fpga realization of low register systolic all-one-polynomial multipliers over gf (2m) and their applications in trinomial multipliers
- Coordinate rotation-based low complexity k-means clustering architecture
- Energy-efficient vlsi realization of binary64 division with redundant number systems
- Hardware-efficient built-in redundancy analysis for memory with various spares
- Reordering tests for efficient fail data collection and tester time reduction
- An fpga-based hardware accelerator for traffic sign detection
- Antiwear leveling design for ssds with hybrid ecc capability
- A fault tolerance technique for combinational circuits based on selective-transistor redundancy
Audio, image & video processing
15 project titles
- A dual-clock vlsi design of h.265 sample adaptive offset estimation for 8k ultra-hd tv encoding
Verification
2 project titles
- Publicly verifiable watermarking for intellectual property protection in fpga design
- Interconnection allocation between functional units and registers in high-level synthesis
Networking on chip (noc)
1 project titles
- Multicast-aware high-performance wireless network-on-chip architectures