2019 – 2020 IEEE VLSI PROJECTS TITLES

About VLSI Networks Project

VLSI full form Very-large-scale integration (VLSI) design is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began when complex semiconductor and communication technologies were being developed. VLSI 2019 2020 IEEE projects in Chennai is a technology by which 10000-1 Million transistors can be fabricated on a single chip. In today’s world VLSI technology is widely used in various branches of Engineering like Voice and Data Communication networks, Digital Signal Processing, Computers, Commercial Electronics, Automobiles, Medicine and many more.
Here at FPGA projects are implemented in vlsi programming either in verilog or VHDL coding using Xilinx software and the bit code is generated from this which can be dumped on fpga kits. Mtech vlsi projects would include the kit implementation which can be done on sparten 3a, sparten 3e and sparten 6 based on the IEEE VLSI paper chosen. We also offer ieee vlsi based projects for ECE final year students and Mtech ECE students.
B.Tech final year projects student can also reach us if they are willing for industrial tool specifications such as cadence orcad, Xilinx FPGA implementation(VHDL Verilog HDL),Tanner EDA,,AVR studio, MATLAB, H-spice, P-spice, Modalism, Network simulator2,Proteaus and many more to follow. Major projects and mini projects in VLSI for ECE students.

IEEE VLSI Projects Title

A Modified Partial Product Generator for Redundant Binary Multipliers
An Efficient Hardware Implementation of Canny Edge Detection Algorithm
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
The Serial Commutator (SC) FFT
An Improved Signed Digit Representation Approach for Constant Vector Multiplication
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
A New XOR-Free Approach for Implementation of Convolutional Encoder
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
Implementation of a PID control PWM Module on FPGA
Built-in Self Testing of FPGAs
An FPGA-Based Cloud System for Massive ECG Data Analysis
Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip
VLSI Implementation of Fully Parallel LTE Turbo Decoders
A High Throughput List Decoder Architecture For Polar Codes
High-Performance NB-LDPC Decoder With Reduction of Message Exchange
A High-Speed FPGA Implementationof an RSD-Based ECC Processor
Low-Power ECG-Based Processor forPredicting Ventricular Arrhythmia
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
Configurable Parallel Hardware Architecture forEfficient Integral Histogram Image Computing
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
A Normal I/O Order Radix-2 FFT Architecture to ProcessTwin Data Streams for MIMO
Unequal-Error-Protection Error Correction Codes for theEmbedded Memories in Digital Signal Processors
A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications