About IEEE NS2 Projects

Welcome to 1 Crore Project Centre Chennai, your gateway to the future of technology and innovation. We take pride in presenting a diverse range of projects based on the IEEE NS2 platform from the years 2018-2019. Our commitment to excellence and relentless pursuit of innovation make us a trusted destination for students and researchers alike. Whether you’re looking to broaden your knowledge or seeking groundbreaking project ideas, our team of experts is here to guide you every step of the way.

Our 2018-2019 IEEE NS2 projects cover a wide spectrum of domains, including wireless communication, network security, and data analysis. At 1 Crore Project Centre Chennai, we understand the importance of staying at the forefront of technology, and our projects reflect that dedication. With access to cutting-edge resources and a supportive learning environment, you can turn your ideas into reality and be a part of the technological advancements that are shaping our world.

Join us today at 1 Crore Project Centre Chennai and embark on a journey of exploration and innovation. Our commitment to nurturing talent and fostering creativity sets us apart as a premier destination for aspiring engineers and researchers. Whether you’re a student looking to kickstart your career or a seasoned professional seeking to expand your expertise, our 2018-2019 IEEE NS2 projects offer a wealth of opportunities. Don’t miss out on the chance to be a part of something extraordinary. Connect with us today and take the first step towards a brighter future in technology.

Low power

• Energy efficient reduce and rank using input adaptive approximations
• Enfire: a spatio-temporal fine-grained reconfigurable hardware
• Sign-magnitude encoding for efficient vlsi realization of decimal multiplication
• Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication
• Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers
• A way-filtering-based dynamic logical-associative cache architecture for low-energy consumption
• Resource-efficient sram-based ternary content addressable memory
• A high-efficiency 6.78-mhz full active rectifier with adaptive time delay control for wireless power transmission

High speed data transmission

• High-speed and low-latency ecc processor implementation over gf(2m) on fpga
• A 2.5-ps bin size and 6.7-ps resolution fpga time-to-digital converter based on delay wrapping and averaging
• Comedi: combinatorial election of diagnostic vectors from detection test sets for logic circuits
• Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding
• A 2.4-3.6-ghz wideband sub-harmonically injection-locked pll with adaptive injection timing alignment technique
• fast automatic frequency calibrator using an adaptive frequency search algorithm
• A 65-nm cmos constant current source with reduced pvt variation
• High-speed parallel lfsr architectures based on improved state-space transformations
• Scalable approach for power droop reduction during scan-based logic bist
• Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations
• Stochastic implementation and analysis of dynamical systems similar to the logistic map

Area efficient/ timing & delay reduction

• Roba multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing
• Vlsi design of 64bit * 64bit high performance multiplier with redundant binary encoding
• A method to design single error correction codes with fast decoding for a subset of critical bits
• Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs
• Efficient soft cancelation decoder architectures for polar codes
• Low-complexity digit-serial multiplier over gf(2m) based on efficient toeplitz block toeplitz matrix-vector product decomposition
• Efficient designs of multiported memory on fpga
• Hybrid lut multiplexer fpga logic architectures
• Fpga realization of low register systolic all-one-polynomial multipliers over gf (2m) and their applications in trinomial multipliers
• Coordinate rotation-based low complexity k-means clustering architecture
• Coordinate rotation-based low complexity k-means clustering architecture
• Energy-efficient vlsi realization of binary64 division with redundant number systems
• Hardware-efficient built-in redundancy analysis for memory with various spares
• Reordering tests for efficient fail data collection and tester time reduction
• An fpga-based hardware accelerator for traffic sign detection
• Antiwear leveling design for ssds with hybrid ecc capability
• A fault tolerance technique for combinational circuits based on selective-transistor redundancy

Audio, image & video processing

• A dual-clock vlsi design of h.265 sample adaptive offset estimation for 8k ultra-hd tv encoding

Verification

• Publicly verifiable watermarking for intellectual property protection in fpga design
• Interconnection allocation between functional units and registers in high-level synthesis

Networking on chip (noc)

• Multicast-aware high-performance wireless network-on-chip architectures