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2015 - 2016 IEEE VLSI Projects Titles

IEEE VLSI Projects Title

  • A Modified Partial Product Generator for Redundant Binary Multipliers
  • An Efficient Hardware Implementation of Canny Edge Detection Algorithm
  • Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
  • A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
  • The Serial Commutator (SC) FFT
  • An Improved Signed Digit Representation Approach for Constant Vector Multiplication
  • High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
  • A New XOR-Free Approach for Implementation of Convolutional Encoder
  • Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
  • Implementation of a PID control PWM Module on FPGA
  • Built-in Self Testing of FPGAs
  • An FPGA-Based Cloud System for Massive ECG Data Analysis
  • Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip
  • VLSI Implementation of Fully Parallel LTE Turbo Decoders
  • A High Throughput List Decoder Architecture For Polar Codes
  • High-Performance NB-LDPC Decoder With Reduction of Message Exchange
  • A High-Speed FPGA Implementationof an RSD-Based ECC Processor
  • Low-Power ECG-Based Processor forPredicting Ventricular Arrhythmia
  • In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
  • Configurable Parallel Hardware Architecture forEfficient Integral Histogram Image Computing
  • Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
  • A Normal I/O Order Radix-2 FFT Architecture to ProcessTwin Data Streams for MIMO
  • Unequal-Error-Protection Error Correction Codes for theEmbedded Memories in Digital Signal Processors
  • A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications

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