2015 - 2016 IEEE VLSI Projects Titles

A Modified Partial Product Generator for Redundant Binary Multipliers

1. A Modified Partial Product Generator for Redundant Binary Multipliers

An Efficient Hardware Implementation of Canny Edge Detection Algorithm

2. An Efficient Hardware Implementation of Canny Edge Detection Algorithm

Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation

3. Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation

10. Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

4. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

The Serial Commutator (SC) FFT

5. The Serial Commutator (SC) FFT

An Improved Signed Digit Representation Approach for Constant Vector Multiplication

6. An Improved Signed Digit Representation Approach for Constant Vector Multiplication

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

7. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

A New XOR-Free Approach for Implementation of Convolutional Encoder

8. A New XOR-Free Approach for Implementation of Convolutional Encoder

Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

9. Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

Implementation of a PID control PWM Module on FPGA

11. Implementation of a PID control PWM Module on FPGA

Built-in Self Testing of FPGAs

12. Built-in Self Testing of FPGAs

An FPGA-Based Cloud System for Massive ECG Data Analysis

13. An FPGA-Based Cloud System for Massive ECG Data Analysis

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

14. Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

VLSI Implementation of Fully Parallel LTE Turbo Decoders

15. VLSI Implementation of Fully Parallel LTE Turbo Decoders

A High Throughput List Decoder Architecture For Polar Codes

16. A High Throughput List Decoder Architecture For Polar Codes

High-Performance NB-LDPC Decoder With Reduction of Message Exchange

17. High-Performance NB-LDPC Decoder With Reduction of Message Exchange

A High-Speed FPGA Implementationof an RSD-Based ECC Processor

18. A High-Speed FPGA Implementationof an RSD-Based ECC Processor

Low-Power ECG-Based Processor forPredicting Ventricular Arrhythmia

19. Low-Power ECG-Based Processor forPredicting Ventricular Arrhythmia

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

20. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

Configurable Parallel Hardware Architecture forEfficient Integral Histogram Image Computing

21. Configurable Parallel Hardware Architecture forEfficient Integral Histogram Image Computing

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

22. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

A Normal I/O Order Radix-2 FFT Architecture to ProcessTwin Data Streams for MIMO

23. A Normal I/O Order Radix-2 FFT Architecture to ProcessTwin Data Streams for MIMO

Unequal-Error-Protection Error Correction Codes for theEmbedded Memories in Digital Signal Processors

24. Unequal-Error-Protection Error Correction Codes for theEmbedded Memories in Digital Signal Processors

A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications

25. A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications