2017 - 2018 IEEE NS2 Projects Titles

Low power

1. Energy efficient reduce and rank using input adaptive approximations

2. Enfire: a spatio-temporal fine-grained reconfigurable hardware

3. Sign-magnitude encoding for efficient vlsi realization of decimal multiplication

4. Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication

5. Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers

6. A way-filtering-based dynamic logical-associative cache architecture for low-energy consumption

7. Resource-efficient sram-based ternary content addressable memory

8. A high-efficiency 6.78-mhz full active rectifier with adaptive time delay control for wireless power transmission

High speed data transmission

1. High-speed and low-latency ecc processor implementation over gf(2m) on fpga

2. A 2.5-ps bin size and 6.7-ps resolution fpga time-to-digital converter based on delay wrapping and averaging

3. Comedi: combinatorial election of diagnostic vectors from detection test sets for logic circuits

4. Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding

5. A 2.4-3.6-ghz wideband sub-harmonically injection-locked pll with adaptive injection timing alignment technique

6. fast automatic frequency calibrator using an adaptive frequency search algorithm

7. A 65-nm cmos constant current source with reduced pvt variation

8. High-speed parallel lfsr architectures based on improved state-space transformations

9. Scalable approach for power droop reduction during scan-based logic bist

10. Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations

11. Stochastic implementation and analysis of dynamical systems similar to the logistic map

Area efficient/ timing & delay reduction

1. Roba multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing

2. Vlsi design of 64bit * 64bit high performance multiplier with redundant binary encoding

3. A method to design single error correction codes with fast decoding for a subset of critical bits

4. Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs

5. Efficient soft cancelation decoder architectures for polar codes

6. Low-complexity digit-serial multiplier over gf(2m) based on efficient toeplitz block toeplitz matrix-vector product decomposition

7. Efficient designs of multiported memory on fpga

8. Hybrid lut multiplexer fpga logic architectures

9. Fpga realization of low register systolic all-one-polynomial multipliers over gf (2m) and their applications in trinomial multipliers

10. Coordinate rotation-based low complexity k-means clustering architecture

11. Coordinate rotation-based low complexity k-means clustering architecture

12. Energy-efficient vlsi realization of binary64 division with redundant number systems

13. Hardware-efficient built-in redundancy analysis for memory with various spares

14. Reordering tests for efficient fail data collection and tester time reduction

15. An fpga-based hardware accelerator for traffic sign detection

16. Antiwear leveling design for ssds with hybrid ecc capability

17. A fault tolerance technique for combinational circuits based on selective-transistor redundancy

Audio, image & video processing

1. A dual-clock vlsi design of h.265 sample adaptive offset estimation for 8k ultra-hd tv encoding


1. Publicly verifiable watermarking for intellectual property protection in fpga design

2. Interconnection allocation between functional units and registers in high-level synthesis

Networking on chip (noc)

1. Multicast-aware high-performance wireless network-on-chip architectures