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2017 - 2018 IEEE NS2 Projects Titles

Low power

  • Energy efficient reduce and rank using input adaptive approximations
  • Enfire: a spatio-temporal fine-grained reconfigurable hardware
  • Sign-magnitude encoding for efficient vlsi realization of decimal multiplication
  • Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication
  • Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers
  • A way-filtering-based dynamic logical-associative cache architecture for low-energy consumption
  • Resource-efficient sram-based ternary content addressable memory
  • A high-efficiency 6.78-mhz full active rectifier with adaptive time delay control for wireless power transmission

High speed data transmission

  • High-speed and low-latency ecc processor implementation over gf(2m) on fpga
  • A 2.5-ps bin size and 6.7-ps resolution fpga time-to-digital converter based on delay wrapping and averaging
  • Comedi: combinatorial election of diagnostic vectors from detection test sets for logic circuits
  • Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding
  • A 2.4-3.6-ghz wideband sub-harmonically injection-locked pll with adaptive injection timing alignment technique
  • fast automatic frequency calibrator using an adaptive frequency search algorithm
  • A 65-nm cmos constant current source with reduced pvt variation
  •  High-speed parallel lfsr architectures based on improved state-space transformations
  • Scalable approach for power droop reduction during scan-based logic bist
  • Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations
  • Stochastic implementation and analysis of dynamical systems similar to the logistic map

Area efficient/ timing & delay reduction

  • Roba multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing
  • Vlsi design of 64bit * 64bit high performance multiplier with redundant binary encoding
  • A method to design single error correction codes with fast decoding for a subset of critical bits
  • Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs
  • Efficient soft cancelation decoder architectures for polar codes
  • Low-complexity digit-serial multiplier over gf(2m) based on efficient toeplitz block toeplitz matrix-vector product decomposition
  • Efficient designs of multiported memory on fpga
  • Hybrid lut multiplexer fpga logic architectures
  • Fpga realization of low register systolic all-one-polynomial multipliers over gf (2m) and their applications in trinomial multipliers
  • Coordinate rotation-based low complexity k-means clustering architecture
  • Coordinate rotation-based low complexity k-means clustering architecture
  • Energy-efficient vlsi realization of binary64 division with redundant number systems
  • Hardware-efficient built-in redundancy analysis for memory with various spares
  • Reordering tests for efficient fail data collection and tester time reduction
  • An fpga-based hardware accelerator for traffic sign detection
  • Antiwear leveling design for ssds with hybrid ecc capability
  • A fault tolerance technique for combinational circuits based on selective-transistor redundancy

Audio, image & video processing

  • A dual-clock vlsi design of h.265 sample adaptive offset estimation for 8k ultra-hd tv encoding

Verification

  • Publicly verifiable watermarking for intellectual property protection in fpga design
  • Interconnection allocation between functional units and registers in high-level synthesis

Networking on chip (noc)

  • Multicast-aware high-performance wireless network-on-chip architectures

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